summaryrefslogtreecommitdiff
path: root/src/arch/arm/miscregs.cc
diff options
context:
space:
mode:
authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-01-24 17:39:48 +0000
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-03-12 10:23:50 +0000
commitf1b7d0afe93497ef55e857cdd7ae9e168970bd65 (patch)
tree113712737092cff6e6227e2eef9c9d32cd1fd628 /src/arch/arm/miscregs.cc
parenta2df8b2f631b82b2830a64206fe50acbf12e7940 (diff)
downloadgem5-f1b7d0afe93497ef55e857cdd7ae9e168970bd65.tar.xz
arch-arm: Adding IPA-Based Invalidating instructions
This patch introduces the TLB IPA-Based invalidating instructions in aarch32. In the entry selection policy the level of translation is not taken into account. This means that no difference stands between (e.g.) TLBIIPAS2 and TLBIPAS2L. Change-Id: Ieeb54665480874d2041056f356d86448c45043cb Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/8822 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
-rw-r--r--src/arch/arm/miscregs.cc20
1 files changed, 15 insertions, 5 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 5a1ef5a6a..e14be7fd4 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -488,7 +488,14 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
break;
}
} else if (opc1 == 4) {
- if (crm == 3) {
+ if (crm == 0) {
+ switch (opc2) {
+ case 1:
+ return MISCREG_TLBIIPAS2IS;
+ case 5:
+ return MISCREG_TLBIIPAS2LIS;
+ }
+ } else if (crm == 3) {
switch (opc2) {
case 0:
return MISCREG_TLBIALLHIS;
@@ -499,6 +506,13 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2)
case 5:
return MISCREG_TLBIMVALHIS;
}
+ } else if (crm == 4) {
+ switch (opc2) {
+ case 1:
+ return MISCREG_TLBIIPAS2;
+ case 5:
+ return MISCREG_TLBIIPAS2L;
+ }
} else if (crm == 7) {
switch (opc2) {
case 0:
@@ -2932,10 +2946,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBIMVAAL)
.writes(1).exceptUserMode();
InitReg(MISCREG_TLBIIPAS2IS)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2LIS)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIALLHIS)
.monNonSecureWrite().hypWrite();
@@ -2946,10 +2958,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBIMVALHIS)
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIIPAS2L)
- .unimplemented()
.monNonSecureWrite().hypWrite();
InitReg(MISCREG_TLBIALLH)
.monNonSecureWrite().hypWrite();