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author | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
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committer | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
commit | 09a6e424ec966d66ec2f8cfba86d4b4141438c5a (patch) | |
tree | 66eddd44448b9b95b4668bd99746572c0e61f998 /src/arch/arm/miscregs.cc | |
parent | 0c29a97ba90b6416014efee232efd9fea2f974d6 (diff) | |
download | gem5-09a6e424ec966d66ec2f8cfba86d4b4141438c5a.tar.xz |
ARM: Implement numcpus bits in L2CTLR register.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
-rw-r--r-- | src/arch/arm/miscregs.cc | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index fc04ce87d..1fecaa38d 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -382,7 +382,19 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) } } } else if (opc1 == 1) { - return MISCREG_L2LATENCY; + switch (crm) { + case 0: + switch (opc2) { + case 2: // L2CTLR, L2 Control Register + return MISCREG_L2CTLR; + default: + warn("Uknown miscregs: crn:%d crm:%d opc1:%d opc2:%d\n", + crn,crm, opc1,opc2); + break; + } + default: + return MISCREG_L2LATENCY; + } } //Reserved for Branch Predictor, Cache and TCM operations break; |