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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-02-22 18:45:30 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-06 13:54:57 +0000 |
| commit | 1fc48cc45471be63a6c7cb4eb2e3a2c13f8f9bf3 (patch) | |
| tree | aa73ba7664e05fa40baf2497985cd02f63a4e524 /src/arch/arm/miscregs.cc | |
| parent | a9b78bcee79a9228d0590091c5f6dfc265e59300 (diff) | |
| download | gem5-1fc48cc45471be63a6c7cb4eb2e3a2c13f8f9bf3.tar.xz | |
dev, arm: Add support for HYP & secure timers
Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10023
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 29 |
1 files changed, 7 insertions, 22 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 8dd56c791..89caa1455 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3176,7 +3176,6 @@ ISA::initializeMiscRegMetadata() .privSecure(!aarch32EL3) .monSecure(0); InitReg(MISCREG_CNTP_TVAL_S) - .unimplemented() .bankedChild() .secure().user(1); InitReg(MISCREG_CNTP_CTL) @@ -3187,7 +3186,6 @@ ISA::initializeMiscRegMetadata() .privSecure(!aarch32EL3) .monSecure(0); InitReg(MISCREG_CNTP_CTL_S) - .unimplemented() .bankedChild() .secure().user(1); InitReg(MISCREG_CNTV_TVAL) @@ -3195,13 +3193,10 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_CNTV_CTL) .allPrivileges(); InitReg(MISCREG_CNTHCTL) - .unimplemented() .hypWrite().monNonSecureRead(); InitReg(MISCREG_CNTHP_TVAL) - .unimplemented() .hypWrite().monNonSecureRead(); InitReg(MISCREG_CNTHP_CTL) - .unimplemented() .hypWrite().monNonSecureRead(); InitReg(MISCREG_IL1DATA0) .unimplemented() @@ -3256,7 +3251,6 @@ ISA::initializeMiscRegMetadata() .privSecure(!aarch32EL3) .monSecure(0); InitReg(MISCREG_CNTP_CVAL_S) - .unimplemented() .bankedChild() .secure().user(1); InitReg(MISCREG_CNTV_CVAL) @@ -3264,7 +3258,6 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_CNTVOFF) .hyp().monNonSecure(); InitReg(MISCREG_CNTHP_CVAL) - .unimplemented() .hypWrite().monNonSecureRead(); InitReg(MISCREG_CPUMERRSR) .unimplemented() @@ -3936,31 +3929,23 @@ ISA::initializeMiscRegMetadata() .hyp().mon() .mapsTo(MISCREG_CNTVOFF); /* 64b */ InitReg(MISCREG_CNTHCTL_EL2) - .unimplemented() - .warnNotFail() - .mon().monNonSecureWrite(0).hypWrite() + .mon().hyp() .mapsTo(MISCREG_CNTHCTL); InitReg(MISCREG_CNTHP_TVAL_EL2) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite() + .mon().hyp() .mapsTo(MISCREG_CNTHP_TVAL); InitReg(MISCREG_CNTHP_CTL_EL2) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite() + .mon().hyp() .mapsTo(MISCREG_CNTHP_CTL); InitReg(MISCREG_CNTHP_CVAL_EL2) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite() + .mon().hyp() .mapsTo(MISCREG_CNTHP_CVAL); /* 64b */ InitReg(MISCREG_CNTPS_TVAL_EL1) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite(); + .mon().privSecure(); InitReg(MISCREG_CNTPS_CTL_EL1) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite(); + .mon().privSecure(); InitReg(MISCREG_CNTPS_CVAL_EL1) - .unimplemented() - .mon().monNonSecureWrite(0).hypWrite(); + .mon().privSecure(); InitReg(MISCREG_IL1DATA0_EL1) .allPrivileges().exceptUserMode(); InitReg(MISCREG_IL1DATA1_EL1) |