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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-11-02 10:33:30 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-11-07 15:22:43 +0000 |
| commit | 07a2fd7ec2fbcd7fcb0b10968dc9c738d67adda2 (patch) | |
| tree | f78a23d35d85c863a93f9c27235fb12921dbe5c6 /src/arch/arm/miscregs.cc | |
| parent | 46a79f7d10f7b8eabd4e3bb45ff50959d04a2571 (diff) | |
| download | gem5-07a2fd7ec2fbcd7fcb0b10968dc9c738d67adda2.tar.xz | |
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are
removing it from gem5 since we were not handling it anyway.
Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13998
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
0 files changed, 0 insertions, 0 deletions