arm: Don't panic when checking coprocessor read/write permissions

Instructions that use the coprocessor interface check the current
program status to determine whether the current context has the
priviledges to read from/write to the coprocessor. Some modes allow
the execution of coprocessor instructions, some others do not allow it,
while some other modes are unexpected (e.g., executing an AArch32 
instruction while being in an AArch64 mode).

Previously we would unconditionally trigger a panic if we were in an 
unexpected mode. This change removes the panic and replaces it
with an Undefined Instruction fault that triggers if and when a 
coprocessor instruction commits in an unexpected mode. This allows
speculative coprocessor instructions from unexpected modes to execute 
but prevents them from gettting committed.

Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>

1 files changed, 15 insertions, 11 deletions

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 09af405ad..20861480b 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2013, 2015-2016 ARM Limited
+ * Copyright (c) 2010-2013, 2015-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -41,6 +41,8 @@
 
 #include "arch/arm/miscregs.hh"
 
+#include <tuple>
+
 #include "arch/arm/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
@@ -1967,11 +1969,12 @@ decodeCP15Reg64(unsigned crm, unsigned opc1)
     return MISCREG_CP15_UNIMPL;
 }
 
-bool
-canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+std::tuple<bool, bool>
+canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
 {
     bool secure = !scr.ns;
-    bool canRead;
+    bool canRead = false;
+    bool undefined = false;
 
     switch (cpsr.mode) {
       case MODE_USER:
@@ -1995,18 +1998,19 @@ canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
         canRead = miscRegInfo[reg][MISCREG_HYP_RD];
         break;
       default:
-        panic("Unrecognized mode setting in CPSR.\n");
+        undefined = true;
     }
     // can't do permissions checkes on the root of a banked pair of regs
     assert(!miscRegInfo[reg][MISCREG_BANKED]);
-    return canRead;
+    return std::make_tuple(canRead, undefined);
 }
 
-bool
-canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
+std::tuple<bool, bool>
+canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
 {
     bool secure = !scr.ns;
-    bool canWrite;
+    bool canWrite = false;
+    bool undefined = false;
 
     switch (cpsr.mode) {
       case MODE_USER:
@@ -2030,11 +2034,11 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
         canWrite =  miscRegInfo[reg][MISCREG_HYP_WR];
         break;
       default:
-        panic("Unrecognized mode setting in CPSR.\n");
+        undefined = true;
     }
     // can't do permissions checkes on the root of a banked pair of regs
     assert(!miscRegInfo[reg][MISCREG_BANKED]);
-    return canWrite;
+    return std::make_tuple(canWrite, undefined);
 }
 
 int