diff options
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-25 18:23:17 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-05-08 15:28:12 +0000 |
| commit | 376f1b2ff7034f4d084a087a68307b11042d2a9d (patch) | |
| tree | 900b593a817104bc9345083f9952bbd3b8444bbf /src/arch/arm/miscregs.cc | |
| parent | 05ee4c5b53cd0eaee5725abf039285156dab2734 (diff) | |
| download | gem5-376f1b2ff7034f4d084a087a68307b11042d2a9d.tar.xz | |
arch-arm: Map ID_x_EL1 registers to AArch32 version
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those
registers must be initialized even when the highest Exception Level is
using AArch64.
Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10361
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 39 |
1 files changed, 26 insertions, 13 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 66159132d..08eb255f3 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -3392,34 +3392,47 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_REVIDR_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_ID_PFR0_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_PFR0); InitReg(MISCREG_ID_PFR1_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_PFR1); InitReg(MISCREG_ID_DFR0_EL1) .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_ID_DFR0); InitReg(MISCREG_ID_AFR0_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_AFR0); InitReg(MISCREG_ID_MMFR0_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_MMFR0); InitReg(MISCREG_ID_MMFR1_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_MMFR1); InitReg(MISCREG_ID_MMFR2_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_MMFR2); InitReg(MISCREG_ID_MMFR3_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_MMFR3); InitReg(MISCREG_ID_ISAR0_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR0); InitReg(MISCREG_ID_ISAR1_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR1); InitReg(MISCREG_ID_ISAR2_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR2); InitReg(MISCREG_ID_ISAR3_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR3); InitReg(MISCREG_ID_ISAR4_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR4); InitReg(MISCREG_ID_ISAR5_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_ID_ISAR5); InitReg(MISCREG_MVFR0_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_MVFR1_EL1) |