diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:52 -0400 |
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committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:52 -0400 |
commit | b520223699f51562140b8cc4a922eae64dffb3e3 (patch) | |
tree | f5a82bf775b332f8817fb3b68502b41fdf663dd4 /src/arch/arm/miscregs.cc | |
parent | 10f82934be924f265af4f10b15ca66106171f770 (diff) | |
download | gem5-b520223699f51562140b8cc4a922eae64dffb3e3.tar.xz |
arm: Use MiscRegIndex rather than int when flattening
Some additional type checking to avoid future issues.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
-rw-r--r-- | src/arch/arm/miscregs.cc | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 4c950a643..d682dc454 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -2034,22 +2034,24 @@ canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) } int -flattenMiscRegNsBanked(int reg, ThreadContext *tc) +flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc) { + int reg_as_int = static_cast<int>(reg); if (miscRegInfo[reg][MISCREG_BANKED]) { SCR scr = tc->readMiscReg(MISCREG_SCR); - reg += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; + reg_as_int += (ArmSystem::haveSecurity(tc) && !scr.ns) ? 2 : 1; } - return reg; + return reg_as_int; } int -flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns) +flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns) { + int reg_as_int = static_cast<int>(reg); if (miscRegInfo[reg][MISCREG_BANKED]) { - reg += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; + reg_as_int += (ArmSystem::haveSecurity(tc) && !ns) ? 2 : 1; } - return reg; + return reg_as_int; } |