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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-05-26 03:21:45 -0400 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2015-05-26 03:21:45 -0400 |
| commit | e590f0d1efe37448d16a86dd03fba1db6c0b4f65 (patch) | |
| tree | 37ecb7c68e57371d03ede73254a18b86bab595f0 /src/arch/arm/miscregs.cc | |
| parent | a22c29b2633475cde9934d04597167f9c4b15cc2 (diff) | |
| download | gem5-e590f0d1efe37448d16a86dd03fba1db6c0b4f65.tar.xz | |
arm: implement the CONTEXTIDR_EL2 system reg.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 729cb4e8b..3a40a27b0 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -1334,6 +1334,8 @@ bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS] = { bitset<NUM_MISCREG_INFOS>(string("11111111110000000100")), // MISCREG_CBAR_EL1 bitset<NUM_MISCREG_INFOS>(string("01010101010000000001")), + // MISCREG_CONTEXTIDR_EL2 + bitset<NUM_MISCREG_INFOS>(string("11111100000000000001")), // Dummy registers // MISCREG_NOP @@ -3343,6 +3345,8 @@ decodeAArch64SysReg(unsigned op0, unsigned op1, switch (crm) { case 0: switch (op2) { + case 1: + return MISCREG_CONTEXTIDR_EL2; case 2: return MISCREG_TPIDR_EL2; } |