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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:16 -0500 |
| commit | c1e1de8d69624b1cf18a13a46e624ad5827954b7 (patch) | |
| tree | 60f11a14eafcc03715c283270edb336e0a44bccc /src/arch/arm/miscregs.cc | |
| parent | 7de7ea3b22e16a6d489a71dc5c54ddba5a5b5a0e (diff) | |
| download | gem5-c1e1de8d69624b1cf18a13a46e624ad5827954b7.tar.xz | |
ARM: Some TLB bug fixes.
Diffstat (limited to 'src/arch/arm/miscregs.cc')
| -rw-r--r-- | src/arch/arm/miscregs.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index a6311e179..776ed94c3 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -153,7 +153,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) } break; case 2: - if (opc2 == 0 && crm == 0) { + if (opc1 == 0 && crm == 0) { switch (opc2) { case 0: return MISCREG_TTBR0; @@ -408,7 +408,7 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) case 13: if (opc1 == 0) { if (crm == 0) { - switch (crm) { + switch (opc2) { case 0: return MISCREG_FCEIDR; case 1: |