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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
| commit | 54a919f22587c75be5e7f0b88d5ec13baba600aa (patch) | |
| tree | 65b9d338a6968f16296e761ab7ce9a4867514b7e /src/arch/arm/miscregs.hh | |
| parent | 6368edb281f162e4fbb0a91744992a25134135f4 (diff) | |
| download | gem5-54a919f22587c75be5e7f0b88d5ec13baba600aa.tar.xz | |
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 86a11d508..453893908 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -354,6 +354,12 @@ namespace ArmISA Bitfield<31> n; EndBitUnion(FPSCR) + BitUnion32(FPEXC) + Bitfield<31> ex; + Bitfield<30> en; + Bitfield<29, 0> subArchDefined; + EndBitUnion(FPEXC) + BitUnion32(MVFR0) Bitfield<3, 0> advSimdRegisters; Bitfield<7, 4> singlePrecision; |