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| author | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-09-04 11:44:42 +0100 |
|---|---|---|
| committer | Anouk Van Laer <anouk.vanlaer@arm.com> | 2018-09-13 09:08:19 +0000 |
| commit | 91295ff980c17efb3ad013b9636017b58e49c071 (patch) | |
| tree | a9e1d23baf777704579d3c1d348eebb6c88f7d71 /src/arch/arm/miscregs.hh | |
| parent | 67f5af9a4da49cd58b35d0f521266051715d9738 (diff) | |
| download | gem5-91295ff980c17efb3ad013b9636017b58e49c071.tar.xz | |
arch-arm: Correction for address size in EL1&0 translation
When doing EL0/1 translation in stage2, the
physical address size will be defined by the
hypervisor (via VTCR_EL2.ps, not TCR.ips).
See D10.2.121 of the ARM ARM.
Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12552
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index c1d5efa10..50e64777c 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1810,6 +1810,7 @@ namespace ArmISA Bitfield<11, 10> orgn0; Bitfield<13, 12> sh0; Bitfield<15, 14> tg0; + Bitfield<18, 16> ps; // Only defined for VTCR_EL2 EndBitUnion(VTCR_t) BitUnion32(PRRR) |