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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-09-13 12:06:13 -0500 |
| commit | 0c29a97ba90b6416014efee232efd9fea2f974d6 (patch) | |
| tree | 935b0361a700936e96e7681dcdb2fc89793fd7df /src/arch/arm/miscregs.hh | |
| parent | e4830ad2eb85b9fef8f6e01b6bcbe34983f1d912 (diff) | |
| download | gem5-0c29a97ba90b6416014efee232efd9fea2f974d6.tar.xz | |
Prefetch: Don't prefetch if address is in the write queue.
Check that we're not currently writing back an address the prefetcher is trying
to prefetch before issuing it. We previously checked the mshrQueue and the cache
itself, but forgot to check the writeBuffer. This fixes a memory corrucption
issue with an L2 prefetcher.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
0 files changed, 0 insertions, 0 deletions