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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
| commit | c1f7bf7f0e97f8470eb4280870244b6b673dbff4 (patch) | |
| tree | c89128e4dff36de237bf7601936f6bb935621e00 /src/arch/arm/miscregs.hh | |
| parent | f245f4937b2f48df17795887bdde9aeaf4476e39 (diff) | |
| download | gem5-c1f7bf7f0e97f8470eb4280870244b6b673dbff4.tar.xz | |
ARM: Add support for VFP vector mode.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 9c781f515..b7521cbd0 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -294,6 +294,32 @@ namespace ArmISA Bitfield<11> wnr; Bitfield<12> ext; EndBitUnion(FSR) + + BitUnion32(FPSCR) + Bitfield<0> ioc; + Bitfield<1> dzc; + Bitfield<2> ofc; + Bitfield<3> ufc; + Bitfield<4> ixc; + Bitfield<7> idc; + Bitfield<8> ioe; + Bitfield<9> dze; + Bitfield<10> ofe; + Bitfield<11> ufe; + Bitfield<12> ixe; + Bitfield<15> ide; + Bitfield<18, 16> len; + Bitfield<21, 20> stride; + Bitfield<23, 22> rMode; + Bitfield<24> fz; + Bitfield<25> dn; + Bitfield<26> ahp; + Bitfield<27> qc; + Bitfield<28> v; + Bitfield<29> c; + Bitfield<30> z; + Bitfield<31> n; + EndBitUnion(FPSCR) }; #endif // __ARCH_ARM_MISCREGS_HH__ |