diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:15 -0500 |
| commit | 98e2315f1c459d8126227b3c598ba4ea9620df7a (patch) | |
| tree | a182189a90b02bead6dcde24745a05062f4ef0bb /src/arch/arm/miscregs.hh | |
| parent | 8466999aefe1da1eade680af3b4d1336d4e04e7f (diff) | |
| download | gem5-98e2315f1c459d8126227b3c598ba4ea9620df7a.tar.xz | |
ARM: Set the value of the MVFR0 and MVFR1 registers.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index b7521cbd0..851044a35 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -320,6 +320,28 @@ namespace ArmISA Bitfield<30> z; Bitfield<31> n; EndBitUnion(FPSCR) + + BitUnion32(MVFR0) + Bitfield<3, 0> advSimdRegisters; + Bitfield<7, 4> singlePrecision; + Bitfield<11, 8> doublePrecision; + Bitfield<15, 12> vfpExceptionTrapping; + Bitfield<19, 16> divide; + Bitfield<23, 20> squareRoot; + Bitfield<27, 24> shortVectors; + Bitfield<31, 28> roundingModes; + EndBitUnion(MVFR0) + + BitUnion32(MVFR1) + Bitfield<3, 0> flushToZero; + Bitfield<7, 4> defaultNaN; + Bitfield<11, 8> advSimdLoadStore; + Bitfield<15, 12> advSimdInteger; + Bitfield<19, 16> advSimdSinglePrecision; + Bitfield<23, 20> advSimdHalfPrecision; + Bitfield<27, 24> vfpHalfPrecision; + Bitfield<31, 28> raz; + EndBitUnion(MVFR1) }; #endif // __ARCH_ARM_MISCREGS_HH__ |