ARM: Implement a function to decode CP15 registers to MiscReg indices.

1 files changed, 88 insertions, 3 deletions

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 99bb57391..8fce26b2c 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -78,13 +78,98 @@ namespace ArmISA
         MISCREG_FPSID,
         MISCREG_FPSCR,
         MISCREG_FPEXC,
-        MISCREG_SCTLR,
+
+        // CP15 registers
+        MISCREG_CP15_START,
+        MISCREG_SCTLR = MISCREG_CP15_START,
+        MISCREG_CP15_UNIMP_START,
+        MISCREG_CTR = MISCREG_CP15_UNIMP_START,
+        MISCREG_TCMTR,
+        MISCREG_MPUIR,
+        MISCREG_MPIDR,
+        MISCREG_MIDR,
+        MISCREG_ID_PFR0,
+        MISCREG_ID_PFR1,
+        MISCREG_ID_DFR0,
+        MISCREG_ID_AFR0,
+        MISCREG_ID_MMFR0,
+        MISCREG_ID_MMFR1,
+        MISCREG_ID_MMFR2,
+        MISCREG_ID_MMFR3,
+        MISCREG_ID_ISAR0,
+        MISCREG_ID_ISAR1,
+        MISCREG_ID_ISAR2,
+        MISCREG_ID_ISAR3,
+        MISCREG_ID_ISAR4,
+        MISCREG_ID_ISAR5,
+        MISCREG_CCSIDR,
+        MISCREG_CLIDR,
+        MISCREG_AIDR,
+        MISCREG_CSSELR,
+        MISCREG_ACTLR,
+        MISCREG_CPACR,
+        MISCREG_DFSR,
+        MISCREG_IFSR,
+        MISCREG_ADFSR,
+        MISCREG_AIFSR,
+        MISCREG_DFAR,
+        MISCREG_IFAR,
+        MISCREG_DRBAR,
+        MISCREG_IRBAR,
+        MISCREG_DRSR,
+        MISCREG_IRSR,
+        MISCREG_DRACR,
+        MISCREG_IRACR,
+        MISCREG_RGNR,
+        MISCREG_ICIALLUIS,
+        MISCREG_BPIALLIS,
+        MISCREG_ICIALLU,
+        MISCREG_ICIMVAU,
+        MISCREG_CP15ISB,
+        MISCREG_BPIALL,
+        MISCREG_BPIMVA,
+        MISCREG_DCIMVAC,
+        MISCREG_DCISW,
+        MISCREG_DCCMVAC,
+        MISCREG_MCCSW,
+        MISCREG_CP15DSB,
+        MISCREG_CP15DMB,
+        MISCREG_DCCMVAU,
+        MISCREG_DCCIMVAC,
+        MISCREG_DCCISW,
+        MISCREG_CONTEXTIDR,
+        MISCREG_TPIDRURW,
+        MISCREG_TPIDRURO,
+        MISCREG_TPIDRPRW,
+
+        MISCREG_CP15_END,
+
+        // Dummy indices
+        MISCREG_NOP = MISCREG_CP15_END,
+        MISCREG_RAZ,
+
         NUM_MISCREGS
     };
 
+    MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
+                               unsigned crm, unsigned opc2);
+
     const char * const miscRegName[NUM_MISCREGS] = {
-        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", 
-        "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "sctlr"
+        "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
+        "spsr_mon", "spsr_und", "spsr_abt",
+        "fpsr", "fpsid", "fpscr", "fpexc",
+        "sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
+        "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
+        "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
+        "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
+        "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
+        "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
+        "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
+        "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
+        "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
+        "cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
+        "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
+        "nop", "raz"
     };
 
     BitUnion32(CPSR)