arm: Don't panic when checking coprocessor read/write permissions

Instructions that use the coprocessor interface check the current
program status to determine whether the current context has the
priviledges to read from/write to the coprocessor. Some modes allow
the execution of coprocessor instructions, some others do not allow it,
while some other modes are unexpected (e.g., executing an AArch32 
instruction while being in an AArch64 mode).

Previously we would unconditionally trigger a panic if we were in an 
unexpected mode. This change removes the panic and replaces it
with an Undefined Instruction fault that triggers if and when a 
coprocessor instruction commits in an unexpected mode. This allows
speculative coprocessor instructions from unexpected modes to execute 
but prevents them from gettting committed.

Change-Id: If2776d5bae2471cdbaf76d0e1ae655f501bfbf01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Rekai Gonzalez Alberquilla <rekai.gonzalezalberquilla@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2281
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Weiping Liao <weipingliao@google.com>

1 files changed, 33 insertions, 8 deletions

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 742295c29..779ead7f4 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2016 ARM Limited
+ * Copyright (c) 2010-2017 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -44,6 +44,7 @@
 #define __ARCH_ARM_MISCREGS_HH__
 
 #include <bitset>
+#include <tuple>
 
 #include "base/bitunion.hh"
 #include "base/compiler.hh"
@@ -1847,13 +1848,37 @@ namespace ArmISA
    EndBitUnion(CPTR)
 
 
-    // Checks read access permissions to coproc. registers
-    bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
-                          ThreadContext *tc);
-
-    // Checks write access permissions to coproc. registers
-    bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
-                           ThreadContext *tc);
+    /**
+     * Check for permission to read coprocessor registers.
+     *
+     * Checks whether an instruction at the current program mode has
+     * permissions to read the coprocessor registers. This function
+     * returns whether the check is undefined and if not whether the
+     * read access is permitted.
+     *
+     * @param the misc reg indicating the coprocessor
+     * @param the SCR
+     * @param the CPSR
+     * @return a tuple of booleans: can_read, undefined
+     */
+    std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
+                                           CPSR cpsr);
+
+    /**
+     * Check for permission to write coprocessor registers.
+     *
+     * Checks whether an instruction at the current program mode has
+     * permissions to write the coprocessor registers. This function
+     * returns whether the check is undefined and if not whether the
+     * write access is permitted.
+     *
+     * @param the misc reg indicating the coprocessor
+     * @param the SCR
+     * @param the CPSR
+     * @return a tuple of booleans: can_write, undefined
+     */
+    std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
+                                             CPSR cpsr);
 
     // Checks read access permissions to AArch64 system registers
     bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,