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authorGabe Black <gblack@eecs.umich.edu>2009-06-26 22:01:34 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-06-26 22:01:34 -0700
commit38d8bc64baab5ef17958d84e9d5fe6d62c31fca3 (patch)
tree58ae32fe8f4d61fbe87b1750207bd375dcb918a4 /src/arch/arm/miscregs.hh
parent7b5386d390a114784fe65efe3884c670c1a9ced8 (diff)
downloadgem5-38d8bc64baab5ef17958d84e9d5fe6d62c31fca3.tar.xz
ARM: Fill out the printReg function.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
-rw-r--r--src/arch/arm/miscregs.hh10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index d939fabcf..42065b0fd 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -55,12 +55,20 @@ namespace ArmISA
enum MiscRegIndex {
MISCREG_CPSR = 0,
+ MISCREG_SPSR,
MISCREG_SPSR_FIQ,
MISCREG_SPSR_IRQ,
MISCREG_SPSR_SVC,
MISCREG_SPSR_UND,
MISCREG_SPSR_ABT,
- MISCREG_FPSR
+ MISCREG_FPSR,
+ NUM_MISCREGS
+ };
+
+ const char * const miscRegName[NUM_MISCREGS] = {
+ "cpsr",
+ "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_und", "spsr_abt",
+ "fpsr"
};
BitUnion32(CPSR)