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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (patch) | |
| tree | c57a005891e10565c9e7552cb90037a667001807 /src/arch/arm/miscregs.hh | |
| parent | 4bf48a11efd7253bdb7a61da42d2bc754033757b (diff) | |
| download | gem5-2178859b76bb13b1d225fc4dffa04d43d2db2e14.tar.xz | |
ARM: Break up condition codes into normal flags, saturation, and simd.
This change splits out the condcodes from being one monolithic register
into three blocks that are updated independently. This allows CPUs
to not have to do RMW operations on the flags registers for instructions
that don't write all flags.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index c506455f8..813b98b69 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -269,7 +269,10 @@ namespace ArmISA // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. - static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMaskF = 0xF0000000; + static const uint32_t CondCodesMaskQ = 0x08000000; + static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) Bitfield<31> ie; // Instruction endianness |