ARM: Convert the CP15 registers from MPU to MMU.

1 files changed, 50 insertions, 13 deletions

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index 81a448fd2..52329a3dc 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -105,14 +105,10 @@ namespace ArmISA
         MISCREG_BPIMVA,
         MISCREG_BPIALLIS,
         MISCREG_BPIALL,
-        MISCREG_MPUIR,
         MISCREG_MIDR,
-        MISCREG_RGNR,
-        MISCREG_DRBAR,
-        MISCREG_DRACR,
-        MISCREG_DRSR,
         MISCREG_CP15_UNIMP_START,
         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
+        MISCREG_TLBTR,
         MISCREG_TCMTR,
         MISCREG_MPIDR,
         MISCREG_ID_PFR0,
@@ -129,21 +125,55 @@ namespace ArmISA
         MISCREG_ID_ISAR3,
         MISCREG_ID_ISAR4,
         MISCREG_ID_ISAR5,
+        MISCREG_PAR,
         MISCREG_AIDR,
         MISCREG_ACTLR,
+        MISCREG_DACR,
         MISCREG_DFSR,
         MISCREG_IFSR,
         MISCREG_ADFSR,
         MISCREG_AIFSR,
         MISCREG_DFAR,
         MISCREG_IFAR,
-        MISCREG_IRBAR,
-        MISCREG_IRSR,
-        MISCREG_IRACR,
         MISCREG_DCIMVAC,
         MISCREG_DCISW,
         MISCREG_MCCSW,
         MISCREG_DCCMVAU,
+        MISCREG_SCR,
+        MISCREG_SDER,
+        MISCREG_NSACR,
+        MISCREG_TTBR0,
+        MISCREG_TTBR1,
+        MISCREG_TTBCR,
+        MISCREG_V2PCWPR,
+        MISCREG_V2PCWPW,
+        MISCREG_V2PCWUR,
+        MISCREG_V2PCWUW,
+        MISCREG_V2POWPR,
+        MISCREG_V2POWPW,
+        MISCREG_V2POWUR,
+        MISCREG_V2POWUW,
+        MISCREG_TLBIALLIS,
+        MISCREG_TLBIMVAIS,
+        MISCREG_TLBIASIDIS,
+        MISCREG_TLBIMVAAIS,
+        MISCREG_ITLBIALL,
+        MISCREG_ITLBIMVA,
+        MISCREG_ITLBIASID,
+        MISCREG_DTLBIALL,
+        MISCREG_DTLBIMVA,
+        MISCREG_DTLBIASID,
+        MISCREG_TLBIALL,
+        MISCREG_TLBIMVA,
+        MISCREG_TLBIASID,
+        MISCREG_TLBIMVAA,
+        MISCREG_PRRR,
+        MISCREG_NMRR,
+        MISCREG_VBAR,
+        MISCREG_MVBAR,
+        MISCREG_ISR,
+        MISCREG_FCEIDR,
+
 
         MISCREG_CP15_END,
 
@@ -160,23 +190,30 @@ namespace ArmISA
     const char * const miscRegName[NUM_MISCREGS] = {
         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
         "spsr_mon", "spsr_und", "spsr_abt",
-        "fpsr", "fpsid", "fpscr", "fpexc", "sev_mailbox",
+        "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1",
+        "sev_mailbox",
         "sctlr", "dccisw", "dccimvac", "dccmvac",
         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
         "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
         "clidr", "ccsidr", "csselr",
         "icialluis", "iciallu", "icimvau",
         "bpimva", "bpiallis", "bpiall",
-        "mpuir", "midr", "rgnr", "drbar", "dracr", "drsr",
-        "ctr", "tcmtr", "mpidr",
+        "midr", "ctr", "tlbtr", "tcmtr", "mpidr",
         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
-        "aidr", "actlr",
+        "par", "aidr", "actlr", "dacr",
         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
-        "irbar", "irsr", "iracr",
         "dcimvac", "dcisw", "mccsw",
         "dccmvau",
+        "scr", "sder", "nsacr", "ttbr0", "ttbr1", "ttbcr",
+        "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw",
+        "v2powpr", "v2powpw", "v2powur", "v2powuw",
+        "tlbiallis", "tlbimvais", "tlbiasidis", "tlbimvaais",
+        "itlbiall", "itlbimva", "itlbiasid",
+        "dtlbiall", "dtlbimva", "dtlbiasid",
+        "tlbiall", "tlbimva", "tlbiasid", "tlbimvaa",
+        "prrr", "nmrr", "vbar", "mvbar", "isr", "fceidr",
         "nop", "raz"
     };