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| author | Matt Horsnell <Matt.Horsnell@arm.com> | 2012-03-01 17:26:31 -0600 |
|---|---|---|
| committer | Matt Horsnell <Matt.Horsnell@arm.com> | 2012-03-01 17:26:31 -0600 |
| commit | 08187e3916fa615444ed61d739ac91e284735a66 (patch) | |
| tree | 27e62a6b77e396b2e848ae5d1a2b368e81add490 /src/arch/arm/miscregs.hh | |
| parent | d907d0ec723538c7969bf8f2f2d6f29439b02985 (diff) | |
| download | gem5-08187e3916fa615444ed61d739ac91e284735a66.tar.xz | |
ARM: Add limited CP14 support.
New kernels attempt to read CP14 what debug architecture is available.
These changes add the debug registers and return that none is currently
available.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 73 |
1 files changed, 72 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 1f84fa4ca..a20fd0c61 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010 ARM Limited + * Copyright (c) 2010-2012 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -86,6 +86,41 @@ namespace ArmISA MISCREG_SCTLR_RST, MISCREG_SEV_MAILBOX, + // CP14 registers + MISCREG_CP14_START, + MISCREG_DBGDIDR = MISCREG_CP14_START, + MISCREG_DBGDSCR_INT, + MISCREG_DBGDTRRX_INT, + MISCREG_DBGTRTX_INT, + MISCREG_DBGWFAR, + MISCREG_DBGVCR, + MISCREG_DBGECR, + MISCREG_DBGDSCCR, + MISCREG_DBGSMCR, + MISCREG_DBGDTRRX_EXT, + MISCREG_DBGDSCR_EXT, + MISCREG_DBGDTRTX_EXT, + MISCREG_DBGDRCR, + MISCREG_DBGBVR, + MISCREG_DBGBCR, + MISCREG_DBGBVR_M, + MISCREG_DBGBCR_M, + MISCREG_DBGDRAR, + MISCREG_DBGBXVR_M, + MISCREG_DBGOSLAR, + MISCREG_DBGOSSRR, + MISCREG_DBGOSDLR, + MISCREG_DBGPRCR, + MISCREG_DBGPRSR, + MISCREG_DBGDSAR, + MISCREG_DBGITCTRL, + MISCREG_DBGCLAIMSET, + MISCREG_DBGCLAIMCLR, + MISCREG_DBGAUTHSTATUS, + MISCREG_DBGDEVID2, + MISCREG_DBGDEVID1, + MISCREG_DBGDEVID, + // CP15 registers MISCREG_CP15_START, MISCREG_SCTLR = MISCREG_CP15_START, @@ -208,15 +243,51 @@ namespace ArmISA NUM_MISCREGS }; + MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1, + unsigned crm, unsigned opc2); + MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2); + const char * const miscRegName[NUM_MISCREGS] = { "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", "mvfr0", "mvfr1", "sctlr_rst", "sev_mailbox", + "DBGDIDR", + "DBGDSCR_INT", + "DBGDTRRX_INT", + "DBGTRTX_INT", + "DBGWFAR", + "DBGVCR", + "DBGECR", + "DBGDSCCR", + "DBGSMCR", + "DBGDTRRX_EXT", + "DBGDSCR_EXT", + "DBGDTRTX_EXT", + "DBGDRCR", + "DBGBVR", + "DBGBCR", + "DBGBVR_M", + "DBGBCR_M", + "DBGDRAR", + "DBGBXVR_M", + "DBGOSLAR", + "DBGOSSRR", + "DBGOSDLR", + "DBGPRCR", + "DBGPRSR", + "DBGDSAR", + "DBGITCTRL", + "DBGCLAIMSET", + "DBGCLAIMCLR", + "DBGAUTHSTATUS", + "DBGDEVID2", + "DBGDEVID1", + "DBGDEVID", "sctlr", "dccisw", "dccimvac", "dccmvac", "contextidr", "tpidrurw", "tpidruro", "tpidrprw", "cp15isb", "cp15dsb", "cp15dmb", "cpacr", |