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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-09-25 17:37:06 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-10-01 15:47:55 +0000 |
| commit | 30746da58f3dbcb37df6214999ad48cb7df1cc4a (patch) | |
| tree | 097ef94a83f7fc0d8bb60aec450b8322f6bee9cc /src/arch/arm/miscregs.hh | |
| parent | 312f44831f45c363bb1a97fdc601cb5efc8d5652 (diff) | |
| download | gem5-30746da58f3dbcb37df6214999ad48cb7df1cc4a.tar.xz | |
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)
Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13066
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 08d6abfac..ab3fc8f7f 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -672,10 +672,10 @@ namespace ArmISA MISCREG_CNTHV_CVAL_EL2, // 602 MISCREG_CNTHV_TVAL_EL2, // 603 + MISCREG_ID_AA64MMFR2_EL1, // 604 // These MISCREG_FREESLOT are available Misc Register // slots for future registers to be implemented. - MISCREG_FREESLOT_1, // 604 - MISCREG_FREESLOT_2, // 605 + MISCREG_FREESLOT_1, // 605 // NUM_PHYS_MISCREGS specifies the number of actual physical // registers, not considering the following pseudo-registers @@ -1388,7 +1388,7 @@ namespace ArmISA "cnthv_ctl_el2", "cnthv_cval_el2", "cnthv_tval_el2", - "freeslot1", + "id_aa64mmfr2_el1", "freeslot2", "num_phys_regs", |