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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
| commit | 38925ff62126e43ea3d44ace39d908ba38dfc1af (patch) | |
| tree | 8c0b37285a3751181aa69f470eb09421f6fc8c5d /src/arch/arm/miscregs.hh | |
| parent | a7e0cbeb36394eec3960dc0e2fb15377880e9e98 (diff) | |
| download | gem5-38925ff62126e43ea3d44ace39d908ba38dfc1af.tar.xz | |
arm: Remove the register mapping hack used when copying TCs
In order to see all registers independent of the current CPU mode, the
ARM architecture model uses the magic MISCREG_CPSR_MODE register to
change the register mappings without actually updating the CPU
mode. This hack is no longer needed since the thread context now
provides a flat interface to the register file. This patch replaces
the CPSR_MODE hack with the flat register interface.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 2dceab70c..02c03a7fc 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -209,7 +209,6 @@ namespace ArmISA MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, - MISCREG_CPSR_MODE, MISCREG_LOCKFLAG, MISCREG_LOCKADDR, MISCREG_ID_PFR1, @@ -311,7 +310,7 @@ namespace ArmISA "pmceid1", "pmc_other", "pmxevcntr", "pmuserenr", "pmintenset", "pmintenclr", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", - "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", + "lockflag", "lockaddr", "id_pfr1", "l2ctlr", // Unimplemented below "tcmtr", |