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| author | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-05-13 17:27:00 -0500 |
|---|---|---|
| committer | Chander Sudanthi <chander.sudanthi@arm.com> | 2011-05-13 17:27:00 -0500 |
| commit | 5299c75e62832aab2e200b22c73865ed9c51b335 (patch) | |
| tree | d439efab806ba35c1bc8cfee0b0a01656a5d513a /src/arch/arm/miscregs.hh | |
| parent | b79650ceaaabb87f9bfe145663e2bfa3281ed7df (diff) | |
| download | gem5-5299c75e62832aab2e200b22c73865ed9c51b335.tar.xz | |
ARM: Better RealView/Versatile EB platform support.
Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index f87cc3ad5..c506455f8 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -174,9 +174,9 @@ namespace ArmISA MISCREG_CPSR_MODE, MISCREG_LOCKFLAG, MISCREG_LOCKADDR, + MISCREG_ID_PFR1, MISCREG_CP15_UNIMP_START, MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, - MISCREG_ID_PFR1, MISCREG_ID_DFR0, MISCREG_ID_AFR0, MISCREG_ID_MMFR1, @@ -236,10 +236,10 @@ namespace ArmISA "pmceid1", "pmc_other", "pmxevcntr", "pmuserenr", "pmintenset", "pmintenclr", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", - "cpsr_mode", "lockflag", "lockaddr", + "cpsr_mode", "lockflag", "lockaddr", "id_pfr1", // Unimplemented below "tcmtr", - "id_pfr1", "id_dfr0", "id_afr0", + "id_dfr0", "id_afr0", "id_mmfr1", "id_mmfr2", "aidr", "adfsr", "aifsr", "dcimvac", "dcisw", "mccsw", |