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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:05 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:05 -0600 |
| commit | 5f59e195d61c9144c817aab4a9179036adad6c9c (patch) | |
| tree | 276229c98c76f736f262448880d3d504b9c20feb /src/arch/arm/miscregs.hh | |
| parent | 371110fb0a8b5c687682c8ce1e1445eee1d3a7bc (diff) | |
| download | gem5-5f59e195d61c9144c817aab4a9179036adad6c9c.tar.xz | |
ARM: Add comment about the organization of the IT state register
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index aa3f47419..2bb1cdb15 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -262,6 +262,12 @@ namespace ArmISA EndBitUnion(CPSR) BitUnion8(ITSTATE) + /* Note that the split (cond, mask) below is not as in ARM ARM. + * But it is more convenient for simulation. The condition + * is always the concatenation of the top 3 bits and the next bit, + * which applies when one of the bottom 4 bits is set. + * Refer to predecoder.cc for the use case. + */ Bitfield<7, 4> cond; Bitfield<3, 0> mask; // Bitfields for moving to/from CPSR |