diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
| commit | 63464d950ec4e8b8f3aa86802ca9fbf1e8c662b6 (patch) | |
| tree | 62269c4404c83a2a371f3d73fc58ff496d472c90 /src/arch/arm/miscregs.hh | |
| parent | 93ce7238bf25b4f75f129aa822c70591a0b15a31 (diff) | |
| download | gem5-63464d950ec4e8b8f3aa86802ca9fbf1e8c662b6.tar.xz | |
ARM: Seperate out the renamable bits in the FPSCR.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 453893908..aa3f47419 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -354,6 +354,10 @@ namespace ArmISA Bitfield<31> n; EndBitUnion(FPSCR) + // This mask selects bits of the FPSCR that actually go in the FpCondCodes + // integer register to allow renaming. + static const uint32_t FpCondCodesMask = 0xF800009F; + BitUnion32(FPEXC) Bitfield<31> ex; Bitfield<30> en; |