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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:28 -0500 |
| commit | 6b6989049383b67a2daef562a0319421ff1a8067 (patch) | |
| tree | a5139ef0015d25e2bbf246ddfed1939c35fbf2d0 /src/arch/arm/miscregs.hh | |
| parent | f926fa77112c53ef8444657e89d4f00f559fd61c (diff) | |
| download | gem5-6b6989049383b67a2daef562a0319421ff1a8067.tar.xz | |
ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.
This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index fc18fa114..2ccd9b4c2 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -170,6 +170,7 @@ namespace ArmISA MISCREG_ID_ISAR3, MISCREG_ID_ISAR4, MISCREG_ID_ISAR5, + MISCREG_CPSR_MODE, MISCREG_CP15_UNIMP_START, MISCREG_TCMTR = MISCREG_CP15_UNIMP_START, MISCREG_ID_PFR1, @@ -233,6 +234,7 @@ namespace ArmISA "pmceid1", "pmc_other", "pmxevcntr", "pmuserenr", "pmintenset", "pmintenclr", "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5", + "cpsr_mode", // Unimplemented below "tcmtr", "id_pfr1", "id_dfr0", "id_afr0", |