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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-24 16:11:38 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-16 09:32:53 +0000 |
| commit | 80427ea030b521779521f57b092bc6b4afc86ab2 (patch) | |
| tree | 257b857eda172dde3fe86d19b1d23bffffed256e /src/arch/arm/miscregs.hh | |
| parent | 8e17f07c295cec854d89cbf427bbd2f8dd915eda (diff) | |
| download | gem5-80427ea030b521779521f57b092bc6b4afc86ab2.tar.xz | |
arch-arm: IMPLEMENTATION DEFINED register
A new pseudo register has been added to the Misc pool. It is the
implementation defined register. This kinds of registers are covered by
the architecture and must be treated differently than UNIMPLEMENTED
registers: their access can be trapped to EL2 (See HCR.TIDCP bit in the
arm arm).
Some previously undecoded registers in c9,c10,c11 have now this register
type.
Change-Id: Ibfc35982470b9dea0ecf39aaa6b1012a21852f53
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7922
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index cb4dcab8c..9bca3d116 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -677,7 +677,7 @@ namespace ArmISA // NUM_PHYS_MISCREGS specifies the number of actual physical // registers, not considering the following pseudo-registers - // (dummy registers), like UNKNOWN, CP15_UNIMPL... + // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL. // Checkpointing should use this physical index when // saving/restoring register values. NUM_PHYS_MISCREGS = 606, // 606 @@ -690,6 +690,11 @@ namespace ArmISA MISCREG_A64_UNIMPL, MISCREG_UNKNOWN, + // Implementation defined register: this represent + // a pool of unimplemented registers whose access can throw + // either UNDEFINED or hypervisor trap exception. + MISCREG_IMPDEF_UNIMPL, + // Total number of Misc Registers: Physical + Dummy NUM_MISCREGS }; @@ -1380,7 +1385,8 @@ namespace ArmISA "cp14_unimpl", "cp15_unimpl", "a64_unimpl", - "unknown" + "unknown", + "impl_defined" }; static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS, |