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authorAndreas Hansson <andreas.hansson@arm.com>2014-10-01 08:05:52 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2014-10-01 08:05:52 -0400
commitb520223699f51562140b8cc4a922eae64dffb3e3 (patch)
treef5a82bf775b332f8817fb3b68502b41fdf663dd4 /src/arch/arm/miscregs.hh
parent10f82934be924f265af4f10b15ca66106171f770 (diff)
downloadgem5-b520223699f51562140b8cc4a922eae64dffb3e3.tar.xz
arm: Use MiscRegIndex rather than int when flattening
Some additional type checking to avoid future issues.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
-rw-r--r--src/arch/arm/miscregs.hh4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index e14722028..3852caee8 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -1859,14 +1859,14 @@ namespace ArmISA
// Uses just the scr.ns bit to pre flatten the misc regs. This is useful
// for MCR/MRC instructions
int
- flattenMiscRegNsBanked(int reg, ThreadContext *tc);
+ flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc);
// Flattens a misc reg index using the specified security state. This is
// used for opperations (eg address translations) where the security
// state of the register access may differ from the current state of the
// processor
int
- flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns);
+ flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns);
// Takes a misc reg index and returns the root reg if its one of a set of
// banked registers