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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-04 20:38:28 -0500 |
| commit | ba8d64520edcecdba28879399523fa6557268e21 (patch) | |
| tree | 1daffd72ae92eb733ba65cc10daa6826780bf906 /src/arch/arm/miscregs.hh | |
| parent | 13574d8b4ee0b8a6e1b5fc7f0feaf2e43952e3df (diff) | |
| download | gem5-ba8d64520edcecdba28879399523fa6557268e21.tar.xz | |
ARM: Add support for MP misc regs and broadcast flushes.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 051cd490e..f87cc3ad5 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -149,6 +149,7 @@ namespace ArmISA MISCREG_V2POWUR, MISCREG_V2POWUW, MISCREG_ID_MMFR0, + MISCREG_ID_MMFR3, MISCREG_ACTLR, MISCREG_PMCR, MISCREG_PMCCNTR, @@ -180,7 +181,6 @@ namespace ArmISA MISCREG_ID_AFR0, MISCREG_ID_MMFR1, MISCREG_ID_MMFR2, - MISCREG_ID_MMFR3, MISCREG_AIDR, MISCREG_ADFSR, MISCREG_AIFSR, @@ -230,7 +230,7 @@ namespace ArmISA "scr", "sder", "par", "v2pcwpr", "v2pcwpw", "v2pcwur", "v2pcwuw", "v2powpr", "v2powpw", "v2powur", "v2powuw", - "id_mmfr0", "actlr", "pmcr", "pmccntr", + "id_mmfr0", "id_mmfr3", "actlr", "pmcr", "pmccntr", "pmcntenset", "pmcntenclr", "pmovsr", "pmswinc", "pmselr", "pmceid0", "pmceid1", "pmc_other", "pmxevcntr", @@ -240,7 +240,7 @@ namespace ArmISA // Unimplemented below "tcmtr", "id_pfr1", "id_dfr0", "id_afr0", - "id_mmfr1", "id_mmfr2", "id_mmfr3", + "id_mmfr1", "id_mmfr2", "aidr", "adfsr", "aifsr", "dcimvac", "dcisw", "mccsw", "dccmvau", |