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| author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:02 +0100 |
|---|---|---|
| committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:02 +0100 |
| commit | c53a57f74f31c2593665bae716c5c3679aab5595 (patch) | |
| tree | 292e4929f35d05d7fac170dacaccd720007269cf /src/arch/arm/miscregs.hh | |
| parent | 49538a71186d98f5440c5db646e23507fc2e38d1 (diff) | |
| download | gem5-c53a57f74f31c2593665bae716c5c3679aab5595.tar.xz | |
arm: add stage2 translation support
Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 84f0fe8d1..f92cc7115 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2015 ARM Limited + * Copyright (c) 2010-2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -1735,10 +1735,12 @@ namespace ArmISA BitUnion32(VTCR_t) Bitfield<3, 0> t0sz; Bitfield<4> s; + Bitfield<5, 0> t0sz64; Bitfield<7, 6> sl0; Bitfield<9, 8> irgn0; Bitfield<11, 10> orgn0; Bitfield<13, 12> sh0; + Bitfield<15, 14> tg0; EndBitUnion(VTCR_t) BitUnion32(PRRR) |