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| author | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
|---|---|---|
| committer | Daniel Johnson <daniel.johnson@arm.com> | 2011-09-13 12:06:13 -0500 |
| commit | cbb23a1d3c3df9d6bed34f50a0193b93319477e6 (patch) | |
| tree | 16d36e66e10d1fcf8b08b1686cedb12cbb65769a /src/arch/arm/miscregs.hh | |
| parent | 52d30813cac76b9dd69ed9c33bb4966f89c5e7a0 (diff) | |
| download | gem5-cbb23a1d3c3df9d6bed34f50a0193b93319477e6.tar.xz | |
ARM: update TLB to set request packet ASID field
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 5e5735de7..1f84fa4ca 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -436,6 +436,11 @@ namespace ArmISA Bitfield<31,30> or7; EndBitUnion(NMRR) + BitUnion32(CONTEXTIDR) + Bitfield<7,0> asid; + Bitfield<31,8> procid; + EndBitUnion(CONTEXTIDR) + BitUnion32(L2CTLR) Bitfield<2,0> sataRAMLatency; Bitfield<4,3> reserved_4_3; |