diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
| commit | d63020717c8a722eb2f5236eacd042cdee78769d (patch) | |
| tree | f53db4e1a39979e80660a7c739f7046d6b8e72c2 /src/arch/arm/miscregs.hh | |
| parent | 981e1dd7eea3661cc2a0f99e783459bdc9fe5bd9 (diff) | |
| download | gem5-d63020717c8a722eb2f5236eacd042cdee78769d.tar.xz | |
ARM: Adds dummy support for a L2 latency miscreg.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index cf9da428a..90b4fd999 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -191,6 +191,7 @@ namespace ArmISA MISCREG_MVBAR, MISCREG_ISR, MISCREG_FCEIDR, + MISCREG_L2LATENCY, MISCREG_CP15_END, |