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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-05-13 17:27:01 -0500 |
| commit | e097c4fb188fafc9cd2253500ab2d056da886c9c (patch) | |
| tree | badbc1cc2849c52a77a211d805af04903223d469 /src/arch/arm/miscregs.hh | |
| parent | 2178859b76bb13b1d225fc4dffa04d43d2db2e14 (diff) | |
| download | gem5-e097c4fb188fafc9cd2253500ab2d056da886c9c.tar.xz | |
ARM: Remove the saturating (Q) condition code from the renamed register.
Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 813b98b69..7f16924f2 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -67,6 +67,7 @@ namespace ArmISA enum MiscRegIndex { MISCREG_CPSR = 0, + MISCREG_CPSR_Q, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, @@ -209,7 +210,7 @@ namespace ArmISA unsigned crm, unsigned opc2); const char * const miscRegName[NUM_MISCREGS] = { - "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", + "cpsr", "cpsr_q", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpscr_qc", "fpscr_exc", "fpexc", "mvfr0", "mvfr1", @@ -269,9 +270,9 @@ namespace ArmISA // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. - static const uint32_t CondCodesMask = 0xF80F0000; + static const uint32_t CondCodesMask = 0xF00F0000; static const uint32_t CondCodesMaskF = 0xF0000000; - static const uint32_t CondCodesMaskQ = 0x08000000; + static const uint32_t CpsrMaskQ = 0x08000000; static const uint32_t CondCodesMaskGE = 0x000F0000; BitUnion32(SCTLR) |