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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (patch) | |
| tree | 58d50fab58de1e9165bfc28986913811b26b9568 /src/arch/arm/miscregs.hh | |
| parent | b93ceef5381b7c84b6887b5299ae81ff48ef45c9 (diff) | |
| download | gem5-05bd3eb4ec3d9fea3dbc46112a47459085d3011c.tar.xz | |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index ddb4ea934..ad8f01dd0 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -67,6 +67,7 @@ namespace ArmISA enum MiscRegIndex { MISCREG_CPSR = 0, + MISCREG_ITSTATE, MISCREG_SPSR, MISCREG_SPSR_FIQ, MISCREG_SPSR_IRQ, @@ -189,7 +190,7 @@ namespace ArmISA unsigned crm, unsigned opc2); const char * const miscRegName[NUM_MISCREGS] = { - "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", + "cpsr", "itstate", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_mon", "spsr_und", "spsr_abt", "fpsr", "fpsid", "fpscr", "fpexc", "mvfr0", "mvfr1", "sctlr_rst", "sev_mailbox", @@ -241,6 +242,14 @@ namespace ArmISA Bitfield<4, 0> mode; EndBitUnion(CPSR) + BitUnion8(ITSTATE) + Bitfield<7, 4> cond; + Bitfield<3, 0> mask; + // Bitfields for moving to/from CPSR + Bitfield<7, 2> top6; + Bitfield<1, 0> bottom2; + EndBitUnion(ITSTATE) + // This mask selects bits of the CPSR that actually go in the CondCodes // integer register to allow renaming. static const uint32_t CondCodesMask = 0xF80F0000; |