summaryrefslogtreecommitdiff
path: root/src/arch/arm/miscregs.hh
diff options
context:
space:
mode:
authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:09 -0500
commit741b24326040cfdd534d05ca46ba4c962bab18f1 (patch)
tree9f5e3279e7c0fbc1114a0fd410281f95d8356a3e /src/arch/arm/miscregs.hh
parent8a7f60194ea24f63759d1985cc04c1fa8b8e2dcb (diff)
downloadgem5-741b24326040cfdd534d05ca46ba4c962bab18f1.tar.xz
ARM: Ignore/warn access to the bpimva registers.
Diffstat (limited to 'src/arch/arm/miscregs.hh')
-rw-r--r--src/arch/arm/miscregs.hh6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index df3d00946..d66ce0f78 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -97,6 +97,7 @@ namespace ArmISA
MISCREG_ICIALLUIS,
MISCREG_ICIALLU,
MISCREG_ICIMVAU,
+ MISCREG_BPIMVA,
MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR,
@@ -136,7 +137,6 @@ namespace ArmISA
MISCREG_RGNR,
MISCREG_BPIALLIS,
MISCREG_BPIALL,
- MISCREG_BPIMVA,
MISCREG_DCIMVAC,
MISCREG_DCISW,
MISCREG_MCCSW,
@@ -161,7 +161,7 @@ namespace ArmISA
"sctlr", "dccisw", "dccimvac", "dccmvac",
"contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr", "clidr",
- "icialluis", "iciallu", "icimvau",
+ "icialluis", "iciallu", "icimvau", "bpimva",
"ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@@ -170,7 +170,7 @@ namespace ArmISA
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "bpiallis",
- "bpiall", "bpimva", "dcimvac", "dcisw", "mccsw",
+ "bpiall", "dcimvac", "dcisw", "mccsw",
"dccmvau",
"nop", "raz"
};