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author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-01-09 10:10:04 +0000 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-02-07 15:13:49 +0000 |
commit | 7798ffb6948d12c7f2bc63dc9a3263bb19aa3297 (patch) | |
tree | 24e2a42dc06b980a86e7763b6b01d9fd7aa372e0 /src/arch/arm/miscregs.hh | |
parent | 633fdd5841d8e7798e1b1158261612a6ad84c812 (diff) | |
download | gem5-7798ffb6948d12c7f2bc63dc9a3263bb19aa3297.tar.xz |
arch-arm: Change function name for banked miscregs
This commit changes the function's name used for retrieving the index of a
security banked register given the flatten index. This will avoid confusion
with flattenRegId, which has a different purpose.
Change-Id: I470ffb55916cb7fc9f78e071a7f2e609c1829f1a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7982
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/miscregs.hh')
-rw-r--r-- | src/arch/arm/miscregs.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 779ead7f4..8cfa01345 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1891,14 +1891,14 @@ namespace ArmISA // Uses just the scr.ns bit to pre flatten the misc regs. This is useful // for MCR/MRC instructions int - flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc); + snsBankedIndex(MiscRegIndex reg, ThreadContext *tc); // Flattens a misc reg index using the specified security state. This is // used for opperations (eg address translations) where the security // state of the register access may differ from the current state of the // processor int - flattenMiscRegNsBanked(MiscRegIndex reg, ThreadContext *tc, bool ns); + snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns); // Takes a misc reg index and returns the root reg if its one of a set of // banked registers |