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| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-07 12:30:08 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2020-02-04 13:39:54 +0000 |
| commit | 98b2d7acc57b664996de528e6d32ae8abaee2b99 (patch) | |
| tree | 21d2559d24dd6506bbfd29819115d1500f9b0b6a /src/arch/arm/miscregs.hh | |
| parent | 465f7d0f56fe47ad5070cc7fcc69bf69cb7d3d82 (diff) | |
| download | gem5-98b2d7acc57b664996de528e6d32ae8abaee2b99.tar.xz | |
arch-arm: AArch64 reg access HCR_EL2.E2H filter
Some AArch64 system registers report UNDEFINED behaviours if accessed
from EL2 or EL3 in a non-EL2 Host enabled (HCR_EL2.E2H == 0) environment.
Examples of these are seen in the Generic Timer system registers,
namely CNTP_CTL_EL02 or CNTKCTL_EL12.
This patch provides an ISA filter for specifying the above condition.
Change-Id: I240f9afdb000faf5d3c9274ba12bd4cc41fe8604
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24664
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/miscregs.hh')
| -rw-r--r-- | src/arch/arm/miscregs.hh | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index 4f522f298..49df42e51 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2019 ARM Limited + * Copyright (c) 2010-2020 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -971,12 +971,18 @@ namespace ArmISA // Hypervisor mode MISCREG_HYP_RD, MISCREG_HYP_WR, + // Hypervisor mode, HCR_EL2.E2H == 1 + MISCREG_HYP_E2H_RD, + MISCREG_HYP_E2H_WR, // Monitor mode, SCR.NS == 0 MISCREG_MON_NS0_RD, MISCREG_MON_NS0_WR, // Monitor mode, SCR.NS == 1 MISCREG_MON_NS1_RD, MISCREG_MON_NS1_WR, + // Monitor mode, HCR_EL2.E2H == 1 + MISCREG_MON_E2H_RD, + MISCREG_MON_E2H_WR, NUM_MISCREG_INFOS }; @@ -1927,11 +1933,11 @@ namespace ArmISA CPSR cpsr); // Checks read access permissions to AArch64 system registers - bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, + bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc); // Checks write access permissions to AArch64 system registers - bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, + bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr, ThreadContext *tc); // Uses just the scr.ns bit to pre flatten the misc regs. This is useful |