arch-arm: Add FP16 support and other primitives to fplib

This changeset:
- extends fplib to support emulation of half-precision floating-point
  (FP16) operations;
- extends fplib to support additional primitives introduced by the Arm
  Scalable Vector Extension (SVE) (fplibExpa, fplibScale,
  fplibTrigMAdd, fplibTrigSMul, fplibTrigSSel);
- adds the FZ16 bit to FPSCR;
- cleans up fplib code by replacing constants with preprocessor macros
  and by adding inline functions to recognise NaNs and infinities.

Change-Id: If8fdb2a5824b478c8310bbc126ec60cc1105f135
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13044
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh
index 198f8c88d..0a862360e 100644
--- a/src/arch/arm/miscregs_types.hh
+++ b/src/arch/arm/miscregs_types.hh
@@ -413,6 +413,7 @@ namespace ArmISA
         Bitfield<12> ixe;
         Bitfield<15> ide;
         Bitfield<18, 16> len;
+        Bitfield<19> fz16;
         Bitfield<21, 20> stride;
         Bitfield<23, 22> rMode;
         Bitfield<24> fz;