diff options
| author | Adrian Herrera <adrian.herrera@arm.com> | 2019-11-08 15:25:21 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-11-18 15:01:01 +0000 |
| commit | 17a0c0b00644c37e9d8539a9de0a02dc213a6834 (patch) | |
| tree | 8ab1d22fcfbc158dafc1a9e92a5d7562c820dc95 /src/arch/arm/miscregs_types.hh | |
| parent | 7e19b26f503435f07dc4b5675061facc521b8c91 (diff) | |
| download | gem5-17a0c0b00644c37e9d8539a9de0a02dc213a6834.tar.xz | |
arch-arm: R/W interface to AArch32 HCR2 misc reg
This patch implements read/write interfaces to HCR2 AArch32 register,
which is mapped to the upper 32 bits of HCR_EL2.
Change-Id: I996023f3ad8233457d19de8a506ebcf106409165
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22832
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/miscregs_types.hh')
| -rw-r--r-- | src/arch/arm/miscregs_types.hh | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/miscregs_types.hh b/src/arch/arm/miscregs_types.hh index 0d6775ec9..20265e294 100644 --- a/src/arch/arm/miscregs_types.hh +++ b/src/arch/arm/miscregs_types.hh @@ -234,8 +234,8 @@ namespace ArmISA BitUnion64(HCR) Bitfield<34> e2h; // AArch64 - Bitfield<33> id; // AArch64 - Bitfield<32> cd; // AArch64 + Bitfield<33> id; + Bitfield<32> cd; Bitfield<31> rw; // AArch64 Bitfield<30> trvm; // AArch64 Bitfield<29> hcd; // AArch64 |