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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
| commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
| tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/arch/arm/nativetrace.cc | |
| parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
| download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz | |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/arch/arm/nativetrace.cc')
| -rw-r--r-- | src/arch/arm/nativetrace.cc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc index 9ba3fa84a..20f13e69e 100644 --- a/src/arch/arm/nativetrace.cc +++ b/src/arch/arm/nativetrace.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011 ARM Limited + * Copyright (c) 2010-2011, 2014 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -116,10 +116,10 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) //CPSR CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); - cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ); - cpsr.c = tc->readIntReg(INTREG_CONDCODES_C); - cpsr.v = tc->readIntReg(INTREG_CONDCODES_V); - cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE); + cpsr.nz = tc->readCCReg(CCREG_NZ); + cpsr.c = tc->readCCReg(CCREG_C); + cpsr.v = tc->readCCReg(CCREG_V); + cpsr.ge = tc->readCCReg(CCREG_GE); newState[STATE_CPSR] = cpsr; changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); @@ -130,7 +130,7 @@ Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) tc->readFloatRegBits(i); } newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) | - tc->readIntReg(INTREG_FPCONDCODES); + tc->readCCReg(CCREG_FP); } void |