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| author | Jose Marinho <jose.marinho@arm.com> | 2017-06-14 12:29:13 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-10 08:36:19 +0000 |
| commit | 22e11ea8dbf6ecb6f1788ae30883106c39aa30fa (patch) | |
| tree | dc8e360512e3e8e76ea1060a814ccc481caf3060 /src/arch/arm/pmu.hh | |
| parent | 457f07c50736ff4ea7fcadc4e766b19e37ffc625 (diff) | |
| download | gem5-22e11ea8dbf6ecb6f1788ae30883106c39aa30fa.tar.xz | |
arch-arm: Support PMU evens in the 0x4000-0x4040 range
ARMv8.1 added a second architected event range, 0x4000-0x4040. Events
in this range are discovered using the high word of PMCEID{0,1}_EL0
Change-Id: I4cd01264230e5da4c841268a7cf3e6bd307c7180
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3960
Diffstat (limited to 'src/arch/arm/pmu.hh')
| -rw-r--r-- | src/arch/arm/pmu.hh | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh index fc5bf74b3..aecdfd84e 100644 --- a/src/arch/arm/pmu.hh +++ b/src/arch/arm/pmu.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2014 ARM Limited + * Copyright (c) 2011-2014, 2017 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -148,7 +148,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { EndBitUnion(PMSELR_t) BitUnion32(PMEVTYPER_t) - Bitfield<9, 0> evtCount; + Bitfield<15, 0> evtCount; // Secure EL3 filtering Bitfield<26> m; @@ -459,10 +459,11 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { /** * Performance counter ID register * - * This register contains a bitmask of available architected + * These registers contain a bitmask of available architected * counters. */ - uint64_t reg_pmceid; + uint64_t reg_pmceid0; + uint64_t reg_pmceid1; /** Remainder part when the clock counter is divided by 64 */ unsigned clock_remainder; |