arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET

Writing a 1 to the Overflow Flag Status register should trigger an
interrupt raise/clear depending on the register we are currently using
(PMOVSCLR for clearing and PMOVSSET for raising).

Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/12531
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

1 files changed, 17 insertions, 0 deletions

diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh
index 61516cffd..ee68272e7 100644
--- a/src/arch/arm/pmu.hh
+++ b/src/arch/arm/pmu.hh
@@ -219,6 +219,11 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
     void raiseInterrupt();
 
     /**
+     * Clear a PMU interrupt.
+     */
+    void clearInterrupt();
+
+    /**
      * Get the value of a performance counter.
      *
      * This method returns the value of a general purpose performance
@@ -269,6 +274,18 @@ class PMU : public SimObject, public ArmISA::BaseISADevice {
      */
     void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);
 
+    /**
+     * Used for writing the Overflow Flag Status Register (SET/CLR)
+     *
+     * This method implements a write to the PMOVSSET/PMOVSCLR registers.
+     * It is capturing change of state in the register bits so that
+     * the overflow interrupt can be raised/cleared as a side effect
+     * of the write.
+     *
+     * @param new_val New value of the Overflow Status Register
+     */
+    void setOverflowStatus(MiscReg new_val);
+
   protected: /* Probe handling and counter state */
     struct CounterState;