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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-01-31 09:52:07 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-08 09:41:25 +0000 |
| commit | b7ce897f1e9545785bde982f72d04830c19d9a30 (patch) | |
| tree | d709f5e4c3f3fe6e530a7c0a66cdfd93a911fe2b /src/arch/arm/pmu.hh | |
| parent | c2b6aac2a8b2ee650a9c220daa6ef75635781f2a (diff) | |
| download | gem5-b7ce897f1e9545785bde982f72d04830c19d9a30.tar.xz | |
arch-arm: Allow ArmPPI usage for PMU
Differently from ArmSPIs, ArmPPI interrupts need to be instantiated by
giving a ThreadContext pointer in the ArmPPIGen::get() method. Since the
PMU is registering the ThreadContext only at ISA startup time, ArmPPI
generation in deferred until the PMU has a non NULL pointer.
Change-Id: I17daa6f0e355363b8778d707b440cab9f75aaea2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/16204
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Diffstat (limited to 'src/arch/arm/pmu.hh')
| -rw-r--r-- | src/arch/arm/pmu.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/pmu.hh b/src/arch/arm/pmu.hh index de931eeb2..f5f521330 100644 --- a/src/arch/arm/pmu.hh +++ b/src/arch/arm/pmu.hh @@ -619,7 +619,7 @@ class PMU : public SimObject, public ArmISA::BaseISADevice { static const RegVal reg_pmcr_wr_mask; /** Performance monitor interrupt number */ - ArmInterruptPin *const interrupt; + ArmInterruptPin *interrupt; /** * List of event types supported by this PMU. |