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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:04 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:04 -0600 |
| commit | 4a1814bd524e7444f57dcd1ea24070fd7b375af3 (patch) | |
| tree | ffab2e2662c660ecd8905efbbf98efafb1ddd2ec /src/arch/arm/predecoder.cc | |
| parent | d4767f440a7a8bfefa0851726b729b8d30a654a5 (diff) | |
| download | gem5-4a1814bd524e7444f57dcd1ea24070fd7b375af3.tar.xz | |
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
Diffstat (limited to 'src/arch/arm/predecoder.cc')
0 files changed, 0 insertions, 0 deletions