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authorAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:20 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-03-17 19:20:20 -0500
commit5480ec798aba313a03c0760d88aeadff1037f48d (patch)
tree85728e51fa46ecc7b969cac5dd23fcd0b4f371e9 /src/arch/arm/predecoder.hh
parent887e9e2b99deaddd669713f47da0642e6f6cb0c5 (diff)
downloadgem5-5480ec798aba313a03c0760d88aeadff1037f48d.tar.xz
ARM: Identify branches as conditional or unconditional and direct or indirect.
Diffstat (limited to 'src/arch/arm/predecoder.hh')
-rw-r--r--src/arch/arm/predecoder.hh7
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index 511bc29bc..08e1676c0 100644
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -128,17 +128,17 @@ namespace ArmISA
outOfBytes = true;
}
- bool needMoreBytes()
+ bool needMoreBytes() const
{
return outOfBytes;
}
- bool extMachInstReady()
+ bool extMachInstReady() const
{
return emiReady;
}
- int getInstSize()
+ int getInstSize() const
{
return (!emi.thumb || emi.bigThumb) ? 4 : 2;
}
@@ -151,6 +151,7 @@ namespace ArmISA
pc.npc(pc.pc() + getInstSize());
predAddrValid = true;
predAddr = pc.pc() + getInstSize();
+ pc.size(getInstSize());
emi = 0;
emiReady = false;
return thisEmi;