summaryrefslogtreecommitdiff
path: root/src/arch/arm/predecoder.hh
diff options
context:
space:
mode:
authorMatt Horsnell <Matt.Horsnell@arm.com>2011-01-18 16:30:05 -0600
committerMatt Horsnell <Matt.Horsnell@arm.com>2011-01-18 16:30:05 -0600
commitb13a79ee717b876e4bc837ba95985abd4d18162f (patch)
treecc11aa8c68e1a22854f2201bf6073e69db88e84e /src/arch/arm/predecoder.hh
parentc98df6f8c2f3a3685fd9210ccaee2fac07e4f604 (diff)
downloadgem5-b13a79ee717b876e4bc837ba95985abd4d18162f.tar.xz
O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.
Diffstat (limited to 'src/arch/arm/predecoder.hh')
-rw-r--r--src/arch/arm/predecoder.hh22
1 files changed, 18 insertions, 4 deletions
diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index 47242b8ff..92aab6e30 100644
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -45,6 +45,8 @@
#ifndef __ARCH_ARM_PREDECODER_HH__
#define __ARCH_ARM_PREDECODER_HH__
+#include <cassert>
+
#include "arch/arm/types.hh"
#include "arch/arm/miscregs.hh"
#include "base/types.hh"
@@ -61,6 +63,8 @@ namespace ArmISA
ExtMachInst emi;
MachInst data;
bool bigThumb;
+ bool emiReady;
+ bool outOfBytes;
int offset;
ITSTATE itstate;
@@ -70,6 +74,8 @@ namespace ArmISA
bigThumb = false;
offset = 0;
emi = 0;
+ emiReady = false;
+ outOfBytes = true;
}
Predecoder(ThreadContext * _tc) :
@@ -103,16 +109,22 @@ namespace ArmISA
moreBytes(0, 0, machInst);
}
+ inline void consumeBytes(int numBytes)
+ {
+ offset += numBytes;
+ assert(offset <= sizeof(MachInst));
+ if (offset == sizeof(MachInst))
+ outOfBytes = true;
+ }
+
bool needMoreBytes()
{
- return sizeof(MachInst) > offset;
+ return outOfBytes;
}
bool extMachInstReady()
{
- // The only way an instruction wouldn't be ready is if this is a
- // 32 bit ARM instruction that's not 32 bit aligned.
- return !bigThumb;
+ return emiReady;
}
int getInstSize()
@@ -123,9 +135,11 @@ namespace ArmISA
//This returns a constant reference to the ExtMachInst to avoid a copy
ExtMachInst getExtMachInst(PCState &pc)
{
+ assert(emiReady);
ExtMachInst thisEmi = emi;
pc.npc(pc.pc() + getInstSize());
emi = 0;
+ emiReady = false;
return thisEmi;
}
};