Automated merge with ssh://hg@repo.m5sim.org/m5

1 files changed, 10 insertions, 3 deletions

diff --git a/src/arch/arm/predecoder.hh b/src/arch/arm/predecoder.hh
index a99e38ce7..08e1676c0 100644
--- a/src/arch/arm/predecoder.hh
+++ b/src/arch/arm/predecoder.hh
@@ -83,6 +83,12 @@ namespace ArmISA
             predAddrValid = false;
         }
 
+        void reset(const ExtMachInst &old_emi)
+        {
+            reset();
+            itstate = old_emi.newItstate;
+        }
+
         Predecoder(ThreadContext * _tc) :
             tc(_tc), data(0)
         {
@@ -122,17 +128,17 @@ namespace ArmISA
                 outOfBytes = true;
         }
 
-        bool needMoreBytes()
+        bool needMoreBytes() const
         {
             return outOfBytes;
         }
 
-        bool extMachInstReady()
+        bool extMachInstReady() const
         {
             return emiReady;
         }
 
-        int getInstSize()
+        int getInstSize() const
         {
             return (!emi.thumb || emi.bigThumb) ? 4 : 2;
         }
@@ -145,6 +151,7 @@ namespace ArmISA
             pc.npc(pc.pc() + getInstSize());
             predAddrValid = true;
             predAddr = pc.pc() + getInstSize();
+            pc.size(getInstSize());
             emi = 0;
             emiReady = false;
             return thisEmi;