arm: Get rid of some register type definitions.

These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.

Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435
Reviewed-on: https://gem5-review.googlesource.com/c/13625
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

1 files changed, 6 insertions, 6 deletions

diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index 095bd3e53..553bac521 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -482,21 +482,21 @@ ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
     memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
 }
 
-ArmISA::IntReg
+RegVal
 ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
 {
     assert(i < 6);
     return tc->readIntReg(ArgumentReg0 + i++);
 }
 
-ArmISA::IntReg
+RegVal
 ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
 {
     assert(i < 8);
     return tc->readIntReg(ArgumentReg0 + i++);
 }
 
-ArmISA::IntReg
+RegVal
 ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
 {
     assert(width == 32 || width == 64);
@@ -515,7 +515,7 @@ ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
     return val;
 }
 
-ArmISA::IntReg
+RegVal
 ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
 {
     return getSyscallArg(tc, i);
@@ -523,14 +523,14 @@ ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
 
 
 void
-ArmProcess32::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
+ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     assert(i < 6);
     tc->setIntReg(ArgumentReg0 + i, val);
 }
 
 void
-ArmProcess64::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val)
+ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
 {
     assert(i < 8);
     tc->setIntReg(ArgumentReg0 + i, val);