diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:18 -0500 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-06-02 12:58:18 -0500 |
commit | 5268067f14d1c0b0df81a6aa688009671926d907 (patch) | |
tree | da19fefa54b8c609880375ec6f53b354dda5250c /src/arch/arm/process.cc | |
parent | 5d5bf8cbc7c0e388a1af80530601ec0422aab60a (diff) | |
download | gem5-5268067f14d1c0b0df81a6aa688009671926d907.tar.xz |
ARM: Fix SPEC2000 benchmarks in SE mode. With this patch all
Spec2k benchmarks seem to run with atomic or timing mode simple
CPUs. Fixed up some constants, handling of 64 bit arguments,
and marked a few more syscalls ignoreFunc.
Diffstat (limited to 'src/arch/arm/process.cc')
-rw-r--r-- | src/arch/arm/process.cc | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index 00a6290c2..555fdf56e 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -362,10 +362,30 @@ ArmLiveProcess::argsInit(int intSize, int pageSize) ArmISA::IntReg ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i) { - assert(i < 4); + assert(i < 6); return tc->readIntReg(ArgumentReg0 + i++); } +uint64_t +ArmLiveProcess::getSyscallArg(ThreadContext *tc, int &i, int width) +{ + assert(width == 32 || width == 64); + if (width == 32) + return getSyscallArg(tc, i); + + // 64 bit arguments are passed starting in an even register + if (i % 2 != 0) + i++; + + // Registers r0-r6 can be used + assert(i < 5); + uint64_t val; + val = tc->readIntReg(ArgumentReg0 + i++); + val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32); + return val; +} + + void ArmLiveProcess::setSyscallArg(ThreadContext *tc, int i, ArmISA::IntReg val) |