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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-08-25 19:10:42 -0500 |
| commit | 54a919f22587c75be5e7f0b88d5ec13baba600aa (patch) | |
| tree | 65b9d338a6968f16296e761ab7ce9a4867514b7e /src/arch/arm/process.cc | |
| parent | 6368edb281f162e4fbb0a91744992a25134135f4 (diff) | |
| download | gem5-54a919f22587c75be5e7f0b88d5ec13baba600aa.tar.xz | |
ARM: Implement CPACR register and return Undefined Instruction when FP access is disabled.
Diffstat (limited to 'src/arch/arm/process.cc')
| -rw-r--r-- | src/arch/arm/process.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc index e7748ad50..e8dda1af0 100644 --- a/src/arch/arm/process.cc +++ b/src/arch/arm/process.cc @@ -78,6 +78,18 @@ ArmLiveProcess::startup() { LiveProcess::startup(); argsInit(MachineBytes, VMPageSize); + for (int i = 0; i < contextIds.size(); i++) { + ThreadContext * tc = system->getThreadContext(contextIds[i]); + CPACR cpacr = tc->readMiscReg(MISCREG_CPACR); + // Enable the floating point coprocessors. + cpacr.cp10 = 0x3; + cpacr.cp11 = 0x3; + tc->setMiscReg(MISCREG_CPACR, cpacr); + // Generically enable floating point support. + FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC); + fpexc.en = 1; + tc->setMiscReg(MISCREG_FPEXC, fpexc); + } } void |